This invention is related to power supply control circuits, and in particular, to a power supply control circuit for use with low voltage CMOS circuitry.
Conventional methods for saving standby power consumed by low voltage CMOS (LVCMOS) circuits, which use MOS transistors to switch on/off power supply buses to low voltage components are implemented using one or more of several techniques. For example, in one technique MOS transistors with low threshold voltages (i.e. 100 to 200 millivolts) are used as bus switching transistors. The disadvantage of this is that the MOS transistors have high subthreshold currents which result in high standby power.
In another technique, MOS transistors with high threshold voltages (i.e. 500 to 700 millivolts) are used as the bus switching transistors. One disadvantage of this is that the transistors have high series resistance which lowers speed. Another disadvantage is that the series resistance is highly sensitive to process variations.
In another technique, NMOS transistors are used to switch the negative or ground power bus (Vss) and PMOS transistors are used to switch the positive power bus (Vdd). The disadvantage here is the large size of the PMOS transistors.
In another technique, the power buses are switched by MOS transistors that are gate-controlled by the same voltages as logic transistors. This also has the disadvantage of high series resistance and corresponding low speed.
Unfortunately, in addition to the disadvantages discussed above other problems may arise when the power supply voltage is decreased, for example, to 1 volt or less. As a result of decreasing the power supply voltage, the threshold of high threshold transistors must be reduced, thus leading to an increase in standby power consumption.
The present invention includes an active/sleep mode power supply control circuit for use with low voltage CMOS circuitry in applications where both high voltage and low voltage power supplies are used. The control circuit includes NMOS transistors with high threshold voltages as switches in both the low voltage power supply and ground buses coupling power to the low voltage circuitry. Incorporating an NMOS switch in both power supply buses allows the size of the control circuit to be small and provides a low series resistance when both switches are switched ON. To achieve the low series resistance, the high threshold voltage NMOS transistors are gate-controlled by a high voltage signal. As a result, the control circuit provides to the low voltage circuits, high speed in the active mode and low power consumption in the sleep mode.
In an embodiment of the present invention a power system for controlling power in a circuit is provided. The power system may be used in circuits having a low voltage supply and a high voltage supply, wherein the low voltage supply powers low voltage circuit components and the high voltage supply powers high voltage circuit components. The power system comprises a first switch coupled between the low voltage supply and the low voltage circuit components, a second switch coupled between the low voltage circuit components and a circuit ground, and a power control circuit coupled to the high voltage supply and the circuit ground and having a control output coupled to the first and second switches, wherein when the control output is in a first state the low voltage supply and the circuit ground are connected to the low voltage circuit components and when the control output is in a second state the low voltage supply and the circuit ground are disconnected from the low voltage circuit components.